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TDA7505
Car radio DSP for advanced signal processing
Features

Full software flexibility with two 24x24 bit DSP cores FM processing AM processing Dolby B noise reduction MP3 and C3 decoding Echo AND noise cancellation Audio processor Special sound effect processor Dual media processing RDS Filter, Demodulator & Decoder 4 + 1 channel ADC, 6 channel DAC CODEC IIC/SPI control busses SAI 6 channel serial audio interface SPDIF interface with sample rate converter Dual core external memory interface Debug interface On-chip PLL Device summary
Order code TDA7505 Package LQFP100 Packing Tray

LQFP100 (14x14x1.4mm)
5V-tolerant 3V I/O interface Multifunction general purpose I/O ports
Description
The TDA7505 is an MPX-sampling DSP for car radio applications.
Table 1.
October 2007
Rev 1
1/38
www.st.com 1
Contents
TDA7505
Contents
1 2 3 4 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.1 4.2 4.3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.3.1 4.3.2 4.3.3 4.3.4 4.3.5 4.3.6 Recommended DC operating conditions . . . . . . . . . . . . . . . . . . . . . . . . 16 Power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 General interface electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 17 High voltage CMOS interface DC electrical characteristics . . . . . . . . . . 17 DSP core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11
SAI interface timing - receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 SAI interface timing - transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 SAI protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 SPDIF receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 SPI interfaces (Buffered SPI, Display SPI, RDS SPI) . . . . . . . . . . . . . . . 20 I2C Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 DRAM/SRAM interface (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Debug port interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.1 5.2 24-bit DSP core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 DSP peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.2.1 5.2.2 5.2.3 5.2.4 5.2.5 Data and program memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Serial audio interface (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Sony/Philips digital interface (S/PDIF) . . . . . . . . . . . . . . . . . . . . . . . . . . 29 I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
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TDA7505 5.2.6 5.2.7 5.2.8 5.2.9 5.2.10 5.2.11 5.2.12 5.2.13 5.2.14
Contents DRAM/SRAM interface (DEMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Debug interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 General purpose input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Asynchronous sample rate converter . . . . . . . . . . . . . . . . . . . . . . . . . . 31 SINCOS co-processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 PLL clock oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 CODEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Radio data system (RDS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Clock scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6
Software features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 AM/FM base band signal processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Generic audio signal processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 TAPE signal processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 CD signal processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Audiophile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Audio decompression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Other . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Functional modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7 8
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
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List of tables
TDA7505
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Recommended DC operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 General interface electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 High voltage CMOS interface DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 17 DSP core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 SAI interface timing - receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 SAI interface timing - transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 SPDIF receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 SPI interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 I2C Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 DRAM timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 DRAM refresh period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 SRAM Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Debug port interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 ASRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Fractional-N PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 ADC electrical characteristics - measurement bandwidth 10Hz to 20kHz . . . . . . . . . . . . . 25 ADC electrical characteristics - measurement bandwidth 10Hz to 53kHz . . . . . . . . . . . . . 25 ADC electrical characteristics - measurement bandwidth 10Hz to 192kHz . . . . . . . . . . . . 25 Level ADC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 DAC Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 FM stereo decoder (SW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Examples of convenient clock schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Example of possible modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
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TDA7505
List of figures
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 LQFP100 pins connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 SAI interface timing - receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 SAI interface timing - transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 SAI protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 SPI interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 SPI clocking scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 I2C Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Debug port serial clock timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Debug port acknowledge timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Debug port data I/O to status timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Debug port read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Debug port DBCK next command after read register timing. . . . . . . . . . . . . . . . . . . . . . . . 24 LQFP100 (14x14x1.4mm) mechanical data and package dimensions. . . . . . . . . . . . . . . . 36
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Overview
TDA7505
1
Overview
The TDA7505 integrates two 75 MIPS DSP cores. One core is used for stereo decoding, noise blanking, weak signal processing, Dolby B, music search and MP3 decoding. The second core is used for audio and sound processing and Echo & Noise cancellation. All functions are realized in SW and thus are flexible on customer request. The device may be controlled by a main micro through either SPI or I2C interface. Through the same pins, but with separate device address (I2C) respectively separate chip select line (SPI) the main micro may communicate with the DSP or with the RDS block. An additional SPI is available allowing a separate communication (e.g. to a display micro). The DSP cores are integrated with their associated data and program memories. DSP0 is declared as master. Its associated peripherals and interfaces are: I2C, SPI1 (Master SPI), SPI2 (Display SPI), Serial Audio Interface (SAI), PLL Oscillator, External Memory Interface (EMI), General Purpose I/O ports (DSP0 GPIO[0..11]), RDS filter and D/A converters. DSP1 is declared as Co-DSP. Its associated peripherals and interfaces are: A/D converters, SPDIF, Sample Rate Converter (SRC) and General Purpose I/O ports (DSP1 GPIO[0..11]). Both DSPs are identical (ST Orpheus core, 75 MHz clock). Only the peripherals and memory configurations are different. The internal communication takes place through a bidirectional 24/10-word exchange interface (XCHG) with complex flag and interrupts capability. The Radio Data System (RDS, respectively RBDS) function is realized via dedicated hardware. It may run fully autonomous without SW intervention. Thus an efficient background mode as well as a low current standby mode is possible. The RDS input is connected to the A/D converter to receive the FM multiplex signal (MPX) automatically. Its output may be configured to I2C or SPI format. The pins are shared with the I2C and SPI1 of DSP0. The device is equipped with a debug and test interface. It allows the SW development with a 100% compatible emulation system. All functions, except RDS, are implemented in SW. Thus, the device may be adapted to customers requirements. This implies the variable implementation of SW modules developed by the customer, ST and third parties. This flexibility also allows the usage for applications others than car radios, e.g.: Boosters.
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TDA7505
Block diagram
2
Figure 1.
Block diagram
Block diagram
CD CC
2 4
analog audio in
Navi. Tel.
2
AM/FM Mpx AM/FMLevel Mpx RDS
3
analog audio out
2
Qdiff.
Diff. Diff.
Qdiff.
Input Source Selector PLL Clock Generator ADCVDD ADCGND AVDD AGND CLK in 8.55MHz AM/FM level ADC
SC Filter SC Filter SC Filter SC Filter SC Filter SC Filter
ADC-ref
Noise Shaper Oversampl. Filter
Noise Shaper Oversampl. Filter
Noise Shaper Oversampl. Filter
DAC-ref DACVDD DACGND RDS Int.
Decimation Audio
Decimation FM/Audio
RDS Filter SINCOS Crystal Oscillator
Demod.
Grp & blk sync., error correction
SPI/ IIC 4
RDSCS P control Display P
6 Ch. Audio Bus
2 receive bit&word clk digital audio in SPDIF audio in SAI 6ch. Receiver SPDIF 2ch. Interface DSP1 Orpheus Core
Including 12 GPIOs
10 word SPI 1 receive stack
IIC / SPI 1 SPI 2 SAI Transmitter
4 3 2 8+3 17
2ch sample rate converter
6 Channel Audio Bus
External Memory Interface
SRAM 4Mx8 DRAM 64Mx4
Debug Interface
AM processing, FM processing, CD compression, Dolby B, MP3
X Ram 4096 X Rom 4096 Y Ram 40969 P Ram 4096 P Rom 16384
DSP0 Orpheus Core Xchg Interface X Ram 4096 Y Ram 4096 P Ram 4096 P Rom 16384
Including 12 GPIOs
INT NRESET 4 4 VDD GND
Audio processing, Sound processing, TAM, Echo & noise cancell.
Debug Interface
Debug/Test 5
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Pin description
TDA7505
3
Table 2.
N 1 2 N 3 4 N
Pin description
Pin description
Name DAC4 DAC5 Name VDD1V8_1 GND1V8_1 Name Type A A Type S S Type Reset state Function Signal output D/A converter (single ended) Signal output D/A converter (single ended) Voltage 1.8V 0V After boot with SPI E1 I2C * E1 I/O EMI E1 Input 5VT Input 5VT Output 2mA PP/OD Input 5VT Input 5VT Input 5VT Output 2mA PP Input 5VT Output 2mA PP Input 5VT Input 5VT Input 5VT Output 2mA PP Input 5VT Input 5VT Output 2mA PP System Reset. A low level applied to NRESET input initializes the IC. SPDIF input source 1 (e.g.: CD) Display SPI SO (slave mode) Display SPI MI (master mode) SPDIF input source 2 (e.g.: MD) Display SPI SI (slave mode) Display SPI MO (master mode) GPIO input GPIO output Display SPI SS slave select DSP0 external interrupt (IRQA) GPIO input GPIO output External clock input for PLL Display SPI clock (slave mode) Display SPI clock (master mode) Function Supply dedicated to the PLL Crystal oscillator input Crystal oscillator output Ground dedicated to the PLL Function Function Digital Supply dedicated to internal logic Digital Ground dedicated to internal logic
5
NRESET SRCCD MISOD output MISOD input SRCMD MOSID input MOSID output DSP0 GPIO0 DSP0 GPIO0 SSD input INT DSP0 GPIO1 DSP0 GPIO1 CLKIN SCKD input SCKD output Name
I
E0
6
I/O
Z
Z
Z
Z
7
I/O Z Z Z Z
8
I/O
Z
Z
Z
Z
9
I/O
Z
Z
Z
Z
N
Type S A A S
Voltage 3.3V AC AC 0V
10 AVDD 11 XTI 12 XTO 13 AGND
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TDA7505 Table 2.
N
Pin description Pin description (continued)
Name
Type
Reset State
After boot with SPI I2C * I/O EMI Input 5VT Output 2mA OD Input 5VT Output 2mA PP Input 5VT Output 2mA OD Output 2mA PP Input 5VT Output 2mA PP RDS SPI CS chip select in RDS bit data GPIO input GPIO output DSP0 external interrupt (IRQA) RDS bit clock RDS Interrupt Output GPIO input GPIO output Function Digital supply dedicated to I/O structures Digital ground dedicated to I/O structures Input 5VT Output 2mA PP In 5VT/Out 2mA OD Input 5VT Output 2mA PP I/O EMI Output 2mA PP/OD Input 5VT Input 5VT Input 5VT Output 2mA PP Input 5VT Output 2mA PP In 5VT/Out 2mA OD Input 5VT Output 2mA PP Input 5VT Input 5VT Output 2mA PP In/Out 2mA PP In/Out 2mA PP In/Out 2mA PP In/Out 2mA PP In/Out 2mA PP In/Out 2mA PP Master/RDS SPI SO (slave m.) Master SPI MI (master mode) I2C Address select line GPIO input GPIO output Master/RDS SPI SI (slave m.) Master SPI MO (master mode) I2C data GPIO input GPIO output Master SPI SS slave select GPIO input GPIO output EMI SRAM Data 0 EMI DRAM Data 0 EMI SRAM Data 1 EMI DRAM Data 1 EMI SRAM Data 2 EMI DRAM Data 2 Master/RDS SPI clock (slave m.) Master SPI clock (master mode) I2C clock GPIO input GPIO output Function Function
RDSCS 14 DSP0 GPIO2 DSP0 GPIO2 INT 15 RDSINT DSP0 GPIO3 DSP0 GPIO3 N Name
I/O
Z
Z
Z
Z
I/O Z Z Z Z
Type S S
Voltage 3.3V 0V
16 VDD3V3_1 17 GND3V3_1 SCKM input SCKM output 18 SCL bi-direct DSP0 GPIO4 DSP0 GPIO4 N Name
I/O Z
0/1
Z Z
Type
Reset state
After boot with SPI I2C *
MISOM output MISOM input 19 ADDR select DSP0 GPIO5 DSP0 GPIO5 MOSIM input MOSIM output 20 SDA bi-direct DSP0 GPIO6 DSP0 GPIO6 SSM input 21 DSP0 GPIO7 DSP0 GPIO7 22 23 24 DSRA<0> DSRA<0> DSRA<1> DSRA<1> DSRA<2> DSRA<2>
I/O Z
0/1
Z Z
I/O Z
0/1
Z Z
Z I/O Z Z Z
I/O I/O I/O
0 0 0
1 1 1
1 1 1
Z Z Z
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Pin description Table 2.
N
TDA7505
Pin description (continued)
Name Type Reset state 0 0 0 0 0 0 0 After boot with SPI 1 1 1 1 1 1 1 I2C * 1 1 1 1 1 1 1 I/O EMI Z Z Z Z Z 0/1 0/1 In/Out 2mA PP In/Out 2mA PP In/Out 2mA PP In/Out 2mA PP In/Out 2mA PP In/Out 2mA PP Output 2mA PP Output 2mA PP Output 2mA PP Output 2mA PP EMI SRAM Data 3 EMI DRAM Data 3 EMI SRAM Data 4 EMI SRAM Data 5 EMI SRAM Data 6 EMI SRAM Data 7 EMI SRAM Address 0 EMI DRAM Address 0 EMI SRAM Address 1 EMI DRAM Address 1 Function Digital Supply dedicated to I/O structures Digital Ground dedicated to I/O structures I/O EMI 0/1 0/1 0/1 0/1 0/1 0/1 0/1 Output 2mA PP Output 2mA PP Output 2mA PP Output 2mA PP Output 2mA PP Output 2mA PP Output 2mA PP Output 2mA PP Output 2mA PP Output 2mA PP Output 2mA PP Output 2mA PP Output 2mA PP Output 2mA PP I/O EMI 0/1 0/1 Output 2mA PP Output 2mA PP Output 2mA PP Output 2mA PP EMI SRAM Address 9 EMI DRAM Address 9 EMI SRAM Address 10 EMI DRAM Address 10 EMI SRAM Address 2 EMI DRAM Address 2 EMI SRAM Address 3 EMI DRAM Address 3 EMI SRAM Address 4 EMI DRAM Address 4 EMI SRAM Address 5 EMI DRAM Address 5 EMI SRAM Address 6 EMI DRAM Address 6 EMI SRAM Address 7 EMI DRAM Address 7 EMI SRAM Address 8 EMI DRAM Address 8 Function Function Function
25
DSRA<3> DSRA<3>
I/O I/O I/O I/O I/O O O Type S S Type
26 DSRA<4> 27 DSRA<5> 28 DSRA<6> 29 DSRA<7> 30 31 N SRA<0> SRA<0> SRA<1> SRA<1> Name
Voltage 3.3V 0V Reset state 0 0 0 0 0 0 0 Reset state 0 0 After boot with SPI 1 1 1 1 1 1 1 I2C * 1 1 1 1 1 1 1
32 VDD3V3_2 33 GND3V3_2 N Name SRA<2> SRA<2> SRA<3> SRA<3> SRA<4> SRA<4> SRA<5> SRA<5> SRA<6> SRA<6> SRA<7> SRA<7> SRA<8> SRA<8> Name SRA<9> SRA<9> SRA<10> SRA<10>
34 35 36 37 38 39 40
O O O O O O O
After boot with SPI 1 1 I2C * 1 1
N
Type
41 42
O O
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TDA7505 Table 2.
N
Pin description Pin description (continued)
Name SRA<11> SRA<11> SRA<12> SRA<12> Name
Type
Reset state 0 0
After boot with SPI 1 1 I2C * 1 1 I/O EMI 0/1 0/1 Output 2mA PP Output 2mA PP Output 2mA PP Output 2mA PP EMI SRAM Address 11 EMI DRAM Address 11 EMI SRAM Address 12 EMI DRAM Address 12 Function Digital Supply dedicated to internal logic Digital Ground dedicated to internal logic and I/O structures Digital Supply dedicated to I/O structures I/O EMI 1 1 0/1 0/1 0/1 Output 2mA PP Output 2mA PP Output 2mA PP Output 2mA PP Output 2mA PP Output 2mA PP Input 5VT Output 2mA PP In 5VT/Out 2mA PP Output 2mA PP Input 5VT Output 2mA PP In 5VT/Out 2mA PP Output 2mA PP Input 5VT Output 2mA PP In 5VT/Out 2mA PP Output 2mA PP Input 5VT Output 2mA PP I/O EMI In 5VT/Out 2mA PP Output 2mA PP Input 5VT Output 2mA PP Multi function I/O EMI SRAM Address 19 GPIO input GPIO output EMI data read strobe EMI data write strobe EMI DRAM CAS EMI SRAM Address 13 EMI SRAM Address 14 EMI SRAM Address 15 GPIO input GPIO output Multi function I/O EMI SRAM Address 16 GPIO input GPIO output Multi function I/O EMI SRAM Address 17 GPIO input GPIO output Multi function I/O EMI SRAM Address 18 GPIO input GPIO output Function Function Function
43 44 N
O O Type S S S Type O O O O I/O
Voltage 1.8V 0V 3.3V Reset state 1 1 0 0 Z After boot with SPI 1 1 1 1 Z I2C * 1 1 1 1 Z
45 VDD1V8_2 46 GND1V8_2 & GND3V3_3
47 VDD3V3_3 N 48 DRD 49 DWR 50 CAS SRA<13> Name
51 SRA<14> SRA<15> 52 DSP0 GPIO8 DSP0 GPIO8 INOUTA SRA<16> 53 DSP1 GPIO0 DSP1 GPIO0 INOUTB SRA<17> 54 DSP1 GPIO1 DSP1 GPIO1 INOUTC SRA<18> 55 DSP1 GPIO2 DSP1 GPIO2 N Name
I/O
Z
Z
Z
0/1
I/O
Z
Z
Z
0/1
I/O
Z
Z
Z
0/1
Type
Reset state
After boot with SPI I2C *
INOUTD SRA<19> 56 DSP1 GPIO3 DSP1 GPIO3
I/O
0/1 Z Z Z
11/38
Pin description Table 2.
N
TDA7505
Pin description (continued)
Name Type Reset state After boot with SPI I2C * I/O EMI In 5VT/Out 2mA PP Output 2mA PP Input 5VT Output 2mA PP In 5VT/Out 2mA PP Output 2mA PP Output 2mA PP Input 5VT Output 2mA PP In 5VT/Out 2mA PP Input 5VT Output 2mA PP In 5VT/Out 2mA PP Input 5VT Output 2mA PP Multi function I/O EMI SRAM Address 20 GPIO input GPIO output Multi function I/O EMI SRAM Address 21 EMI DRAM RAS GPIO input GPIO output Multi function I/O GPIO input GPIO output Multi function I/O GPIO input GPIO output Function Digital Supply dedicated to I/O structures Digital Ground dedicated to I/O structures I/O EMI In 5VT/Out 2mA PP Input 5VT Output 2mA PP In 5VT/Out 2mA PP Input 5VT Out 2mA PP Input 5VT Output 2mA PP Output 2mA PP Input 5VT Output 2mA PP I/O EMI Input 5VT Out 2mA PP Input 5VT Output 2mA PP Debug input Chip status 0 GPIO input GPIO output Multi function I/O GPIO input GPIO output Multi function I/O Debug clock Chip status 1 GPIO input GPIO output Debug output GPIO input GPIO output Function Function Function
INOUTE SRA<20> 57 DSP1 GPIO4 DSP1 GPIO4 INOUTF SRA<21> 58 RAS DSP1 GPIO5 DSP1 GPIO5 INOUTG 59 DSP1 GPIO6 DSP1 GPIO6 INOUTH 60 DSP1 GPIO7 DSP1 GPIO7 N Name
I/O
0/1 Z Z Z 0/1
I/O Z Z Z
I/O
Z
Z
Z
Z
I/O
Z
Z
Z
Z
Type S S Type Reset state
Voltage 3.3V 0V After boot with SPI I2C *
61 VDD3V3_4 62 GND3V3_4 N Name
INOUTI 63 DSP1 GPIO8 DSP1 GPIO8 64 INOUTJ DBCK OS1 65 DSP0/1 GPIO9 DSP0/1 GPIO9 DBOUT 66 DSP0/1 GPIO10 DSP0/1 GPIO10 N Name
I/O I/O
Z Z
Z Z
Z Z
Z Z
I/O Z
0
0
0
I/O
Z Reset state
1
1
1
After boot with SPI I2C *
Type
DBIN OS0 67 DSP0/1 GPIO11 DSP0/1 GPIO11
I/O Z
0
0
0
12/38
TDA7505 Table 2.
N
Pin description Pin description (continued)
Name
Type I I I/O Type S S Type A A A A A A A A A Type S S Type A A A A A A A A A Type S S
Reset state E1 E1 0
After boot with SPI E1 E1 0 I2C * E1 E1 0 I/O EMI E1 E1 0 Input Input In 5VT/Out 2mA PP Mode select (Debug0/1, Test) Mode select (Debug0/1, Test) Multi function I/O Function Digital Supply dedicated to internal logic Digital substrate Ground Function Function
68 Debug/Test_Sel0 69 Debug/Test_Sel1 70 INOUTK N Name
Voltage 1.8V 0V
71 VDD1V8_3 72 GNDSUB_D N Name
73 LEVEL_AM/FM 74 MPX_AM+ 75 MPX_AM/FM76 MPX_FM+ 77 MPX_RDS 78 Navi79 Navi+ 80 Phone81 Phone+ N Name
Signal input to level ADC (single ended) Signal input tuner AM (quasi differential) Signal input tuner common ground (quasi differential) Signal input tuner FM (quasi differential) Signal input background tuner (for RDS) single ended Signal input from navigation system (differential) Signal input from navigation system (differential) Signal input from Telephone (differential) Signal input from Telephone (differential) Voltage 0V 3.3V Function Analog Ground dedicated to the A/D converter Analog Supply dedicated to the A/D converter Function ADC reference voltage decoupling Signal right input from CD-changer (differential) Signal right input from CD-changer (differential) ADC reference voltage decoupling Signal left input from CD-changer (differential) Signal left input from CD-changer (differential) ADC reference voltage decoupling Signal right input from cassette (single ended) Signal left input from cassette (single ended) Voltage 0V 3.3V Function Analog substrate Ground Analog Supply dedicated to the D/A converter.
82 ADCGND 83 ADCVDD N Name
84 ADCREF3 85 CD_R+ 86 CD_R87 ADCREF2 88 CD_L89 CD_L+ 90 ADCREF1 91 CC_R 92 CC_L N Name
93 GNDSUB_A 94 DACVDD
13/38
Pin description Table 2.
N
TDA7505
Pin description (continued)
Name Type A Type S Type A A A A
Type:
Function DAC reference voltage decoupling Voltage 0V Function Analog Ground dedicated to the D/A converter. Function Signal output D/A converter (single ended) Signal output D/A converter (single ended) Signal output D/A converter (single ended) Signal output D/A converter (single ended)
0: logic low output 1: logic high output E0: logic low input E1: logic high input PP: push-pull OD: open drain 5VT: 5 volt tolerant Schmitt-trigger on all inputs
95 DACREF N Name
96 DACGND N Name
97 DAC0 98 DAC1 99 DAC2 100 DAC3
S: Supply pin I: Digital Input pin O: Digital Output pin A: Analog pin
Z: high impedance (Input mode of bi-directional pin) *) I2C Master boot mode, using multiplexed debug interface (pin15: INT/RDSINT = 1, pin21: SSM = 0, pin52: SRA15 = 0)
Figure 2.
LQFP100 pins connection (top view)
DAC3 DAC2 DAC1 DAC0 DACGND DACREF DACVDD GNDSUB_A CC_L CC_R ADCREF1 CD_L+ CD_LADCREF2 CD_RCD_R+ ADCREF3 ADCVDD ADCGND Phone+ PhoneNavi+ NaviMPX_RDS MPX_FM+ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
DSP0 GPIO0 DSP0 GPIO1
DSP0 GPIO2 DSP0 GPIO3 DSP0 GPIO4 DSP0 GPIO5 DSP0 GPIO6 DSP0 GPIO7
DAC4 DAC5 VDD1V8_1 GND1V8_1 NRESET SRCCD/MISOD SRCMD/MOSID INT/SSD CLKIN/SCKD AVDD XTI XTO AGND RDSCS INT/RDSINT VDD3V3_1 GND3V3_1 SCL/SCKM ADDR/MISOM SDA/MOSIM SSM DSRA<0> DSRA<1> DSRA<2> DSRA<3>
CODEC
SPDIF DSPI Debug/Test PLL RDS Bootsel0
TDA7505
SAI/SPDIF
BSPI/I2C Bootsel1 Bootsel2 EMI
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
MPX_AM/FMMPX_AM+ LEVEL_AM/FM GNDSUB_D VDD1V8_3 INOUTK Debug/Test_Sel1 Debug/Test_Sel0 DBIN_OS0 DSP0/1 GPIO11 DBOUT DSP0/1 GPIO10 DBCK_OS1 DSP0/1 GPIO9 INOUTJ DSP1 GPIO8 INOUTI GND3V3_4 VDD3V3_4 DSP1 GPIO7 INOUTH INOUTG DSP1 GPIO6 INOUTF/SRA<21>/RAS DSP1 GPIO5 INOUTE/SRA<20> DSP1 GPIO4 INOUTD/SRA<19> DSP1 GPIO3 INOUTC/SRA<18> DSP1 GPIO2 INOUTB/SRA<17> DSP1 GPIO1 DSP1 GPIO0 INOUTA/SRA<16> SRA<15> DSP0 GPIO8 SRA<14>
14/38
DSRA<4> DSRA<5> DSRA<6> DSRA<7> SRA<0> SRA<1> VDD3V3_2 GND3V3_2 SRA<2> SRA<3> SRA<4> SRA<5> SRA<6> SRA<7> SRA<8> SRA<9> SRA<10> SRA<11> SRA<12> VDD1V8_2 GND1V8_2/GND3V3_3 VDD3V3_3 DRD DWR CAS/SRA<13>
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
TDA7505
Electrical specifications
4
4.1
Electrical specifications
Absolute maximum ratings
Table 3.
Symbol VDD1V8 VDD3V3 AVDD DACVDD ADCVDD Power supplies digital I/O Analog DAC ADC Analog input or output voltage Digital input or output voltage, 5V tolerant Top Tstg Operating temperature range Storage temperature Normal Fail-safe(3)
(2)
Absolute maximum ratings
Parameter Value -0.5 to +1.95 -0.5 to +3.6 -0.5 to +3.6(1) -0.5 to +3.6(1) -0.5 to +3.6(1) -0.5 to (AVDD+0.5) (1) -0.5 to 6.3 -0.5 to 3.8 -40 to 85 -55 to 150 Unit V V V V V V V V C C
1. The maximum difference in the voltage of AVDD, DACVDD, ADCVDD, analog inputs and analog outputs must not exceed 0.5V. Warning: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. 2. During Normal Mode operation VDD3 is always available as specified. 3. During Fail-save Mode operation VDD3 may be not available.
4.2
Thermal data
Table 4.
Symbol Rth j-amb Tj Rth j-case
1. In still air 2. Measured on top side of the package
Thermal data
Parameter Thermal resistance junction to ambient (1) Operating junction temperature Thermal junction to case
(2)
Value 55 125 10
Unit C/W C C/W
15/38
Electrical specifications
TDA7505
4.3
4.3.1
Table 5.
Symbol VDD1V8 VDD3V3 AVDD DACVDD ADCVDD
Electrical characteristics
Recommended DC operating conditions
Recommended DC operating conditions
Parameter Digital supply voltage I/O supply voltage Analog supply voltage D/A supply voltage A/D supply voltage Test condition Min. 1.7 3.15 3.15 3.15 3.15 Typ. 1.8 3.3 3.3 3.3 3.3 Max. 1.9 3.49 3.49 3.49 3.49 Unit V V V V V
4.3.2
Table 6.
Symbol Idd Idio IDAC IADC
Power consumption
Power consumption
Parameter Maximum current Maximum current Maximum current Maximum current Test condition Digital power supply @ 1.8V Digital IO power supply @ 3.3V DAC analog power supply @ 3.3V ADC analog power supply @ 3.3V Min. Typ. 195 6 22 43 Max. Unit mA mA mA mA
Note: 75MHz internal DSP clock, all CODEC channels enabled at Tamb = 25 C
4.3.3
Table 7.
Symbol FOSC FEXT FCLKIN
Oscillator characteristics
Oscillator characteristics
Parameter Crystal oscillator frequency(1) External oscillator frequency External oscillator frequency connected through pin connected through pin XTI(1) CLKIN(2) Test condition Min. Typ. 8.55 75 80 Max. Unit MHz MHz MHz
1. RDS works only with 8.55Mhz quartz or alternative with 74.1MHz applied externally on XTI pin. 2. An alternative clock input (pin CLKIN) can be used for PLL to adjust the audio sampling rate. RDS can work in parallel with the 8.55MHz quartz.
16/38
TDA7505
Electrical specifications
4.3.4
Table 8.
Symbol lil lih Ioz IozFT Ilatchup Vesd
General interface electrical characteristics
General interface electrical characteristics
Parameter Test condition Min. Typ. Max. 1 1 1 1 1 200 2000 7 Unit A A A A A mA V
Low level input current without pull-up Vi = 0V(1) device High level input current without pull-up Vi = VDD3V3 (1) device Tri-state output leakage without pull up/down device 5V tolerant tri-state output leakage without pull up/down device I/O latch-up current Electrostatic protection Vo = 0V or VDD3V3(1) Vo = 0V or VDD3V3(1) Vo = 5.5V Vi < 0V, Vi > VDD3V3 Leakage, 1A (2)
1. The leakage currents are generally very small, <1nA. The value given here, 1 A, is a maximum that can occur after an electrostatic stress on the pin. 2. Human Body Model.
4.3.5
Table 9.
Symbol Vil Vih Vhyst Vol Voh
High voltage CMOS interface DC electrical characteristics
High voltage CMOS interface DC electrical characteristics
Parameter Low Level Input Voltage High Level Input Voltage Schmitt trigger hysteresis Low level output Voltage High level output Voltage Test condition 3.0V1. Takes into account 200mV voltage drop in both supply lines. 2. X is the source/sink current under worst-case conditions and is depicted for every I/O or output pin in the pin description.
4.3.6
Table 10.
Symbol Fdsp Tres
DSP core
DSP core
Parameter DSP clock frequency Reset signal low state duration Test condition Min. Typ. 75 1 Max. Unit MHz s
17/38
Electrical specifications
TDA7505
4.4
SAI interface timing - receiver
Figure 3. SAI interface timing - receiver
Valid
SDI0-2
LRCKR
Valid
SCKR
(RCKP=0)
t lrckrs tsdis tsckrl
t lrckrh tsdih tsckrh tsckr
Table 11.
Timing TDSP(1) tsckr tlrckrs tlrckrh tsdid tsdih tsckrh tsckrl
SAI interface timing - receiver
Description Internal DSP clock period (typical 1/75MHz) Minimum clock cycle LRCKR setup time LRCKR hold time SDI setup time SDI hold time Minimum SCKR high time Minimum SCKR low time 6 TDSP TDSP TDSP TDSP TDSP 0.35 tsckr 0.35 tsckr Min Typ 13.33 Max Unit ns ns ns ns ns ns ns ns
1. TDSP = DSP master clock cycle time = 1/Fdsp
4.5
SAI interface timing - transmitter
Figure 4. SAI interface timing - transmitter
Valid
SDO0-2
LRCKT
Valid
SCKT
(TCKP=0)
t lrckts t dt tscktl
t lrckth
tsckth tsckt
18/38
TDA7505 Table 12.
Timing TDSP(1) tsckt tlrckts tlrckth tdt tsckth tscktl
Electrical specifications SAI interface timing - transmitter
Description Internal DSP clock period (typical 1/75MHz) Minimum clock cycle LRCKT setup time LRCKT hold time SCKT active edge to data out valid Minimum SCKT high time Minimum SCKT low time 6 TDSP TDSP TDSP TDSP 0.35 tsckr 0.35 tsckr Min Typ 13.33 Max Unit ns ns ns ns ns ns ns
1. TDSP = DSP master clock cycle time = 1/Fdsp
4.6
SAI protocol
Figure 5. SAI protocol
LEFT CHANNEL RIGHT CHANNEL
SCKX SCKX LRCKX LRCKX LRCKX
XCKP = 0
XCKP = 1 XREL = 0 XLRS = 0 XREL = 0 XLRS = 1 XREL = 1 XLRS = 0
1 0 15 14 13 6 31 30 29 5 4 3 2 1 0 15 14 13 6 31 30 29 5 4 3 2 1 0 15 14 13 31 30 29
SDY0-2
XDIR = 0
SDY0-2
XDIR = 1
14 15 0 30 31
1
2
9 10 11 12 13 14 15 0 25 26 27 28 29 30 31
1
2
9 10 11 12 13 14 15 0 25 26 27 28 29 30 31
1
2
Notes: 1) X = R for receiver 2) Y = I for receiver
X = T for transmitter Y = O for transmitter
4.7
Table 13.
Symbol fspdif
SPDIF receiver
SPDIF receiver
Parameter Input sampling rate Input precision with direct interface to DSP Input precision with interface to ASRC Test condition Fdsp = 75 MHz Min 32 Typ Max 96 24 20 Unit kHz bit bit
19/38
Electrical specifications
TDA7505
4.8
SPI interfaces (Buffered SPI, Display SPI, RDS SPI)
Figure 6. SPI interfaces
SS
V alid
M ISO M O SI
V alid
SCK
(CP O L=0,CPH A=0)
t setup tdtr tsclkl tsssetup
t hold t sshold tsclkh tsclk
Table 14.
Symbol TDSP
SPI interfaces
Description Internal DSP clock period (typical 1/75MHz) Min Typ 13.33 Max Unit ns
Master mode tsclk tdtr tsetup thold tsclkh tsclkl Clock cycle SCK edge to MOSI valid MISO setup time MISO hold time SCK high time SCK low time 12 TDSP 40 16 9 0.5 tsclk 0.5 tsclk 40 25 ns ns ns ns ns ns ns ns
tsssetup SS setup time tsshold SS hold time
Slave mode tsclk tdtr tsetup thold tsclkh tsclkl Clock cycle SCK edge to MOSI valid MOSI setup time MOSI hold time SCK high time SCK high low 12 TDSP 40 16 9 0.5 tsclk 0.5 tsclk 40 20 ns ns ns ns ns ns ns ns
tsssetup SS setup time tsshold SS hold time
20/38
TDA7505 Figure 7. SPI clocking scheme
SS SCK
(CPOL=0,CPHA=0)
Electrical specifications
SCK SCK
(CPOL=0,CPHA=1)
(CPOL=1,CPHA=0)
SCK MISO MOSI
(CPOL=1,CPHA=1)
MSB
6
5
4
3
2
1
0
4.9
I2C Timing
Figure 8. I2C Timing
Table 15.
Symbol
I2C Timing
Parameter Test condition Standard mode I2C bus Min. Max. 100 - Fast mode I2C bus Unit Min. 0 1.3 Max. 400 - kHz ms
FSCL tBUF
SCLl clock frequency Bus free between a STOP and Start Condition Hold time (repeated) START condition. After this period, the first clock pulse is generated LOW period of the SCL clock HIGH period of the SCL clock Set-up time for a repeated start condition DATA hold time Rise time of both SDA and SCL signals Cb in pF
0 4.7
tHD:STA tLOW tHIGH tSU:STA tHD:DAT tR
4.0 4.7 4.0 4.7 0 -
- - - - - 1000
0.6 1.3 0.6 0.6 0 20+0.1Cb
- - - - 0.9 300
ms ms ms ms ms ns
21/38
Electrical specifications Table 15.
Symbol
TDA7505
I2C Timing (continued)
Parameter Test condition Standard mode I2C bus Min. Max. 300 - - 400 Fast mode I2C bus Unit Min. 20+0.1Cb 0.6 100 - Max. 300 - - 400 ns ms ns pF
tF tSU;STO tSU:DAT Cb
Fall time of both SDA and SCL signals Set-up time for STOP condition Data set-up time Capacitive load for each bus line
Cb in pF
- 4 250 -
4.10
Table 16.
Symbol Tacc0 Tacc0 Tacc1 Tacc1
DRAM/SRAM interface (EMI)
DRAM timing
Parameter Fast DRAM access time Fast DRAM access time Slow DRAM access time Slow DRAM access time Test condition EDTM=0, 16 bit word EDTM=0, 24 bit word EDTM=1, 16 bit word EDTM=1, 24 bit word Min. Typ. 17 23 24 32 Max. Unit Tdsp Tdsp Tdsp Tdsp
Table 17.
Symbol Tref
DRAM refresh period
Parameter DRAM refresh period Test condition Min. 469 Typ. Max. 782 Unit Tdsp
Table 18.
Symbol Tacc
SRAM Timing
Parameter SRAM access time Test condition Min. 2 Typ. Max. 9 Unit Tdsp
4.11
Debug port interface
Table 19.
No. 1 2 3 4 5 6 7
Debug port interface
Characteristics (Fdsp = 75MHz) Min. Max. 2 2 40 40 200 5*TDSP 40 Unit ns ns ns ns ns ns ns
DBCK rise time DBCK fall time DBCK low DBCK high DBCK cycle time DBRQN asserted to DBOUT (ACK) asserted DBCK high to DBOUT valid
22/38
TDA7505 Table 19.
No. 8 9 10
Electrical specifications Debug port interface (continued)
Characteristics (Fdsp = 75MHz) DBCK high to DBOUT invalid DBIN valid to DBCK low (set-up) DBCK low to DBIN invalid (hold) DBOUT (ACK) asserted to first DBCK high DBOUT (ACK) assertion width 11 12 Last DBCK low of read register to first DBCK high of next command Last DBCK low to DBOUT invalid (hold) DBSEL setup to DBCK Min. 3 15 3 2*TDSP 5*TDSP - 3 7*TDSP + 10 3 TDSP 5*TDSP + 7 Max. Unit ns ns ns ns ns ns ns ns
Figure 9.
Debug port serial clock timing
(1) (3) (2)
DBCK (input)
(5)
(4)
D02AU1363
Figure 10. Debug port acknowledge timing
DBRQN (input)
(6)
DBOUT (output)
D02AU1364
(ACK)
Figure 11. Debug port data I/O to status timing
DBCK (input) DBOUT (output) (9) DBIN (input)
(Note 1) Note: 1 High Impedance, external pull-down resistor
(Last)
(10)
D02AU1365
23/38
Electrical specifications Figure 12. Debug port read timing
DBCK (input) (7) DBOUT (output)
Note: 1 High Impedance, external pull-down resistor
TDA7505
(Last)
(Note 1)
(8)
(12)
D02AU1369
Figure 13. Debug port DBCK next command after read register timing
DBCK (input)
(NEXT COMMAND)
(11)
D02AU1370
Table 20.
Symbol
ASRC
Parameters Test conditions 20 Hz-20 kHz, full scale, 16 bit inp. 20 Hz-20 kHz, Full scale, 20 bit inp. min typ -95 -98 -95 -95 -105 -98 98 120 0 No input signal decimation Input signal decimation by 2 32 32 96 48 48 max Unit dB dB dB dB dB dB dB dB deg kHz kHz kHz
Total harmonic distortion + noise, unweighted, THD+N Fsin / Fsout = 0.82 (36 kHz 44.1 kHz)
1 kHz, full scale, 16 bit inp. 15 kHz, full scale, 16 bit inp. 1 kHz, full scale, 20 bit inp. 15 kHz, full scale, 20 bit inp.
DR
Dynamic range, A-weighted, dithered input, Fsin / Fsout = 0.82 (36 kHz 44.1 kHz) Interchannel phase deviation Input sample rate range Input sample rate Output sample rate range
1 kHz, -60 dB, 16 bit inp. 1 kHz, -60 dB, 16 bit inp.
IPD
Digital filter fp Rp fs Rs Passband Frequency Passband Ripple Stopband Corner Frequency Stopband Attenuation @ fs 0-0.4110 Fsin -0.01 0.5510 -120 0.4110 +0.01 Fsin dB Fsin dB
Table 21.
Symbol fVCO
Fractional-N PLL
Parameter VCO output frequency Test condition Min. 130 Typ. Max. 310 Unit MHz
24/38
TDA7505 Table 22.
Symbol Vin fs DR(1) SNR THD+N Ri ICL(2)
Electrical specifications ADC electrical characteristics - measurement bandwidth 10Hz to 20kHz (Tamb = 25C, ADCVDD = 3.3V, A-weighted filter.)
Parameter Input voltage dynamic range Sampling rate Dynamic range Signal to noise ratio Test condition Single ended mode Differential mode Audio mode -60dB analog input 1kHz; -3dB analog input 84 84 88 88 -85 45 80 -95 -80 Min. 0.5 1 48 Typ. Max. Unit Vrms kHz dB dB dB k dB
Total harmonic distortion + noise 1kHz; -3dB analog input Input impedance Interchannel isolation @ fs = 44.1kHz Full scale input @ 1kHz
1. The specified value is obtained by adding 60dB to THD+N measure @ full scale -60dB 2. ICL can be influenced by external anti alias filter
Table 23.
Symbol Vin fs DR
(1)
ADC electrical characteristics - measurement bandwidth 10Hz to 53kHz (Tamb = 25C, ADCVDD = 3.3V)
Parameter Input voltage dynamic range Sampling rate Dynamic range Signal to noise ratio FM-mode -60dB analog input 1kHz; -3dB analog input 80 80 -80 Test condition Min. 0.5 192 Typ. Max. Unit Vrms kHz dB dB dB
SNR THD+N
Total harmonic distortion + noise 1kHz; -3dB analog input
1. The specified value is obtained by adding 60dB to THD+N measure @ full scale -60dB
Table 24.
Symbol Vin fs DR(1) SNR
ADC electrical characteristics - measurement bandwidth 10Hz to 192kHz (Tamb = 25C, AVDD = 3.3V)
Parameter Input voltage dynamic range Sampling rate Dynamic range Signal to noise ratio FM-mode for spike and RDS -60dB analog input 1kHz; -3dB analog input 60 60 Test condition Min. 0.5 384 Typ. Max. Unit Vrms kHz dB dB
1. The specified value is obtained by adding 60dB to THD+N measure @ full scale -60dB
Table 25.
Symbol Vin THD THD+N SNR
Level ADC electrical characteristics (Tamb = 25C, AVDD = 3.3V)
Parameter Input voltage range Total harmonic distortion Total harmonic distortion + noise Signal to noise ratio Test condition Min. 0 -57 -46 46 Typ. Max. 2.5 Unit V dB dB dB
25/38
Electrical specifications Table 26.
Symbol THD+N THD SNR DR(1) NF(2) ICL Xtlk IGM
TDA7505
DAC Performance (Tamb = 25C, DACVDD = 3.3V, measurement bandwidth 10Hz to 20kHz)
Parameter Test condition Min. Typ. -90 -90 100 100 -100 -90 -90 0.1 Max. Unit dB dB dB dB dBV dB dB dB
Total harmonic distortion + noise 1kHz; -1dBFS, flat Total harmonic distortion Signal to noise ratio Dynamic range Noise floor Interchannel isolation Crosstalk Interchannel gain mismatch 1kHz; -1dBFS, flat 1kHz;IEC61606 A-weighted RMS 1kHz; -60dBFS; IEC61606 A-weighted RMS IEC61606 A-weighted RMS 1kHz; 0dBFS 1kHz; 0dBFS 1kHz; 0dBFS
1. The specified value is obtained by adding 60dB to THD+N measure @ full scale -60dB 2. With 00h input
Table 27.
Symbol a_ch
FM stereo decoder (SW) (Tamb = 25C, ADCVDD = 3.3V, measurement bandwidth 10Hz to 20kHz, A-Weighted Filter.)
Parameter Channel separation -3dB analog input 1kHz; -3dB analog input; mono Test condition Min. Typ. >40 -80 86 Max. Unit dB dB dB
(THD+N) Total harmonic distortion SNR Signal to noise ratio
26/38
TDA7505
Functional description
5
Functional description
The TDA7505 is broken up into three distinct blocks. One block contains the two DSP Cores and their associated peripherals. The second contains the analog modules ADC with input multiplexer and level adjust and the DAC. The third module contains the RDS processing: filter, demodulator, decoder with error correction and the I2C/SPI interface with data buffer and interrupts output.
5.1
24-bit DSP core
The two DSP cores are used to process the audio and FM/AM data, coming from the ADC, or any kind of digital data coming via SPDIF or SAI. After the digital signal processing these data are sent to the DAC for analog conversion. Functions such as volume, tone, balance, and fader control, as well as spatial enhancement and general purpose signal processing may be performed by the DSP0. When FM/AM mode is selected, DSP1 is fully devoted to AM/FM processing. Nevertheless it can be used for any kind of different application, when a different input source is selected. Some capabilities of the DSPs are listed below:

Single cycle multiply and accumulate with convergent rounding and condition code generation 2 x 56-bit Accumulators Double precision multiply Scaling and saturation arithmetic 48-bit or 2 x 24-bit parallel moves 64 interrupt vector locations Fast or long interrupts possible Programmable interrupt priorities and masking Repeat instruction and zero overhead DO loops Hardware stack capable of nesting combinations of 7 DO loops or 15 interrupts/subroutines Bit manipulation instructions possible on all registers and memory locations, also Jump on bit test 4 pin serial debug interface Debug access to all internal registers, buses and memory locations 5 word deep program address history FIFO Hardware and software breakpoints for both program and data memory accesses Debug Single stepping, Instruction injection and Disassembly of program memory
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Functional description
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5.2
DSP peripherals
There are a number of peripherals that are tightly coupled to the two DSP Cores. Some of the peripherals are connected to DSP 0 others are connected to DSP 1.

4k x 24-Bit Program RAM for DSP0 16k x 24-Bit mask programmable Program ROM for DSP0 4k x 24-Bit X-Data RAM for DSP0 4k x 24-Bit Y-Data RAM for DSP0 4k x 24-Bit Program RAM for DSP1 16k x 24-Bit mask programmable Program ROM for DSP1 4k x 24-Bit X-Data RAM for DSP1 4k x 24-Bit mask programmable X-Data ROM for DSP1 4k x 24-Bit Y-Data RAM for DSP1 6 channel Serial Audio Interface (SAI) 2 channel SPDIF receiver with sampling rate conversion I2C and SPI interfaces XCHG Interface for DSP to DSP communication External Memory Interface (DRAM/SRAM) for time-delay and traffic information Debug Port for both DSPs General-purpose Input/Output lines Asynchronous Sample Rate Converter SINCOS co-processor PLL Clock Oscillator ADCs, ADC input multiplexer and DACs (see Section 5.2.12: CODEC on page 32)
5.2.1
Data and program memories
Both DSP0 and DSP1 have data and program memories attached to them. Each memory type is described below:
X-RAM
This is a 24-Bit Single Port SRAM used for storing coefficients. The 16-Bit XRAM address, XABx(15:0) is generated by the Address Generation Unit of the DSP core. The 24-Bit XRAM Data, XDBx(23:0), may be written to and read from the Data ALU of the DSP core.
X-ROM
This is a 24-Bit Single Port mask programmable ROM used for storing coefficients. The 16Bit XRAM address, XABx(15:0) is generated by the Address Generation Unit of the DSP core. The 24-Bit XRAM Data, XDBx(23:0), may be read from the Data ALU of the DSP core.
Y-RAM
This is a 24-Bit Single Port SRAM used for storing coefficients. The 16-Bit address, YABx(15:0) is generated by the Address Generation Unit of the DSP core. The 24-Bit Data, YDBx(23:0), is written to and read from the Data ALU of the DSP core.
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Functional description
Program RAM
This is a 24-Bit Single Port SRAM used for storing and executing program code. The 16-Bit PRAM Address, PABx(15:0) is generated by the Program Address Generator of the DSP core for Instruction Fetching, and by the AGU in the case of the Move Program Memory (MOVEM) Instruction. The 24-Bit PRAM Data (Program Code), PDBx(23:0), can only be written to using the MOVEM instruction. During instruction fetching the PDBx Bus is routed to the Program Decode Controller of the DSP core for instruction decoding.
Program ROM
This is a 24-Bit Single Port mask programmable ROM used for storing and executing program code. Additionally the boot loader SW is placed here. Essentially this consists of reading the data via I2C, SPI or EMI interface and store it in PRAM, XRAM and YRAM. The 16-Bit PROM Address, PABx(15:0) is generated by the Program Address Generator of the DSP core for Instruction Fetching, and by the AGU in the case of the Move Program Memory (MOVEM) Instruction. The 24-Bit PROM Data (Program Code), PDBx(23:0), can only be read but not written. During instruction fetching the PDBx Bus is routed to the Program Decode Controller of the DSP core for instruction decoding.
5.2.2
Serial audio interface (SAI)
The SAI is used to deliver digital audio to the device from an external source. Once processed by the device, either it can be returned through this interface or sent to the DAC for D/A conversion. The features of the SAI are listed below:

3 Synchronized Stereo Data Transmission Lines 3 Synchronized Stereo Data Reception Lines Master and Slave operating mode: clock lines can be both master and slave. Receive and Transmit Data Registers have two locations to hold left and right data.
5.2.3
Serial peripheral interface (SPI)
The DSP core requires a serial interface to receive commands and data over the LAN. During an SPI transfer, data are transmitted and received simultaneously. A serial clock line synchronizes shifting and sampling of the information on the two serial data lines. A slave select line allows individual selection of a slave SPI device. When an SPI transfer occurs an 8-bit word is shifted out through one data pin while another 8-bit word is simultaneously shifted in through a second data pin. The central elements in the SPI system are the shift register and the read data buffer. The system is single buffered in the transfer direction and has a 10 word buffer in the receive direction (only master SPI; the display SPI is single word buffered only).
5.2.4
Sony/Phillips digital interface (S/PDIF)
The S/PDIF receiver is a serial digital audio interface. It receives and decodes serial audio data according to one of the following standards: AES/EBU, IEC 958, S/PDIF, and EIAJ CP340 in a frequency range from 32kHz up to 96kHz. The transfer protocol provides two audio data channels. There is a direct output connected to Asynchronous Sample Rate Converter. Left and right 20 bit audio-channels and sample clock are provided.
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Functional description
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5.2.5
I2C interface
The inter Integrated Circuit bus is a single bidirectional two-wire bus used for efficient inter IC control. The device is compliant with the I2C specification including the highs peed (400 kHz) mode. Every component hooked up to the I2C bus has its own unique address whether it is a CPU, memory or some other complex function chip. Each of these chips can act as a receiver and /or transmitter on its functionality. The device may act as master or as slave.
XCHG interface (DSP to DSP exchange interface)
The Exchange Interface peripheral provides bidirectional communication between DSP0 and DSP1. Both 24 bit word data and four bit Flag data can be exchanged. A FIFO is utilized for received data. It minimizes the number of times an Exchange Interrupt Service Routine would have to be called if multi-word blocks of data were to be received. The Transmit FIFO is in effect the Receive FIFO of the other DSP and is written directly by the transmitting DSP. The features of the XCHG are listed below:

10 Word XCHG FIFO on DSP0 to transfer data to DSP1 24 Word XCHG FIFO on DSP1 to transfer data to DSP0 Four Flags for each XCHG for DSP to DSP signaling Condition flags can optionally trigger interrupts on both DSPs
5.2.6
DRAM/SRAM interface (DEMI)
The External DRAM/SRAM Interface is viewed as a memory mapped peripheral of both DSP cores. Data transfers are performed by moving data into/from data registers. The control is exercised by polling status flags in the control/status register or by servicing interrupts. This can be done by both DSP cores. The features of the DEMI (Dual core Extended Memory Interface) are listed below:

Data bus width fixed at 4 bits for DRAM and 8 bits for SRAM Data word length 16 or 24 bits for DRAM Data word length 8 or 16 or 24 bits for SRAM 13 DRAM address lines means 226 = 256M bit addressable DRAM Refresh rate for DRAM can be chosen among eight divider factors SRAM relative addressing mode; 222 = 32M bit addressable SRAM Four SRAM Timing choices Two Read Offset Registers
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Functional description
5.2.7
Debug interface
A multiplexed Debug Port is available for the DSP Cores. The debug logic is contained in the core design of the DSP. The features of the Debug Port are listed below:

Breakpoint Logic Trace Logic Single stepping Instruction Injection Program Disassembly
5.2.8
General purpose input/output
The DSP requires a set of external general purpose input/output lines, and a reset line. These signals are used by external devices to signal events to the DSP. The GPIO lines are implemented as DSP 's peripherals. The GPIO lines are grouped in Port A, connected to DSP 0, and Port B, connected to DSP1.
5.2.9
Asynchronous sample rate converter
The ASRC, embedded in the device, offers a fully digital stereo asynchronous sample rate conversion of digital audio sources to the device's internal sample frequency. This solves the problem of mixing audio sources with different sample rates. The ASRC is able to do both up- and down-sampling. There is no need to explicitly program the input and output sample rates, as the ASRC solves this problem with an automatic Digital Ratio Locked Loop. In case of down sampling, an internal low pass filter limits the bandwidth. Thus any down folding products are avoided. The ASRC is intended for applications up to 20 bit input word width. Digital Audio Sources can be applied in general Serial Audio Interface format (3 wires) as well as in AES/EBU, IEC 958, S/PDIF and EIAJ CP-340 format (1 wire). An interface to the DSP core offers the possibility of interrupt controlled sample delivery. Furthermore, a programmable Control/Status Register inside the ASRC allows a great variety of adjustments and status information. The ASRC is intended for applications - - - up to 20 bit input and 24 bit output word width, 32kHz to 96kHz sample rate for input signal (SPDIF Receiver features) 32kHz to 48kHz sample rate for output signal.
5.2.10
SINCOS co-processor
The SINCOS is a cordic-based co-processor for calculation of sine and cosine without using DSP resources.
5.2.11
PLL clock oscillator
The PLL Clock Oscillator can accept an external clock at CLKIN or it can be configured to run with an internal oscillator when a crystal is connected across pins XTI & XTO. There is an input divide block IDF (1 -> 32) at the XTI clock input and a multiply block MF (9 -> 128)
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Functional description
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in the PLL loop. Hence the PLL can multiply the external input clock by a ratio MF/IDF to generate the internal clock. This allows the internal clock to be within 1 MHz of any desired frequency even when XTI is much greater than 1 MHz. It is recommended that the input clock is not divided down to less than 1 MHz as this reduces the Phase Detector's update rate. The clocks to the DSP can be selected to be either the VCO output divided by 2 to 16, or be driven by the XTI pin directly. The crystal oscillator and the PLL will be gated off when entering the power-down mode (by setting a register on DSP0).
5.2.12
CODEC
The CODEC is composed of four plus one A/D mono converters and three D/A stereo converters. Two channels of the ADC can operate both in audio mode and in FM mode. When in audio mode, it converts the audio bandwidth from 20Hz to 20KHz. The A to D is a third order Sigma-Delta converter with 20-bit resolution. When in FM mode, the converted bandwidth is up to 192KHz. Additionally a lower resolution A to D converter is implemented. It is used to convert the level signal of the tuner. Alternatively it may be used to convert voice signals. The DAC is a second order multi bits Sigma-Delta converter accepting 24 bits input data. All the reference voltages are generated inside the chip but they have to be decoupled with external capacitors.
5.2.13
Radio data system (RDS)
The RDS block is a hardware cell able to deliver the RDS frames through a dedicated serial interface. An RDS quality signal is also available. This block needs to be initialized at reset by the DSP, after that it works in background and does not need any further DSP support. RDS is made of 57kHz filter, demodulator, decoder with error correction and an I2C/SPI programmable interface with data buffer and interrupt output. Due to its own interface, it may be considered as an independent function. Thus the module has a separate RDS I2C device address as well as a separate chip select line for the RDS SPI. Only the pins are shared with the DSP interfaces.
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Functional description
5.2.14
Clock scheme
Due to the programmable PLL oscillator, the clock scheme is very flexible. The customer may choose the clock frequency according to the application needs. However one should take into account several constraints:
The RDS module needs a crystal frequency of 8.55 MHz or alternative an external 74.1MHz Oscillator. However the PLL may be supplied by an external clock reference and the crystal in parallel may drive the RDS module. The CODEC (A/D and D/A) module needs a clock of 512 times the audio sample rate (Fs). The audio sample rate (Fs) should be close to 44.1 kHz. This allows CD quality. Higher sample rates will reduce the number of DSP clock cycles per Fs and hence will reduce the available MIPS. The DSP core clock frequency may not exceed 76 MHz In a car radio system the second and third system clock harmonics (DSP clock and CODEC clock) should be outside the radio frequency bands.

Two examples of convenient clock schemes are shown in the following table: Table 28. Examples of convenient clock schemes
Clock scheme Fxtal Fcomp Fvco Fdsp Fcodec Fs 8.55 MHz Fxtal / 4 2.14 MHz Fcomp * 106 226.58 MHz Fvco / 3 75.53 MHz Fvco / 10 22.66 MHz 44.25 kHz Alternative(1) 74.1 MHz Fxtal/21 3.53 MHz Fcomp * 64 225.8 MHz Fvco / 3 75.28 MHz Fvco / 10 22.58 MHz 44.11 kHz
1. External clock oscillator used
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Software features
TDA7505
6
Software features
A great flexibility is guaranteed by the two programmable DSP cores. A list of the main software functions, which can be implemented in the TDA7505, is enclosed hereafter:
6.1
AM/FM base band signal processing

FM weak signal processing Integrated 19 kHz Pilot tone filter De-emphasis Stereo blend Variable high cut Flexible noise cancellation Flexible multipath detector Asynchronous demodulation allows the usage of any sample rate
6.2
Generic audio signal processing

Loudness Bass, treble, fader control Volume control Distortion Limiting Premium Equalization Soft mute
6.3
TAPE signal processing

Dolby B Noise Reduction Automatic Music Search
6.4
CD signal processing
Dynamic Range Compression
6.5
Audiophile

Parametric Equalization Crossover Channel Delays Center Channel Imaging Output Audio Noise Reduction
6.6
Audio decompression
MP3 including C3 block decoder
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Software features
6.7
Other

Voice compression/decompression for traffic information storage Echo and noise canceling for mobile phone connection
6.8
Functional modes
The SW defines the whole functionality of the device, except RDS. Although ST is able to provide a complete set of SW, the customer may implement his own SW or may use third party SW. This allows a flexible adaptation to the application needs. The concept allows the parallel processing of two independent audio sources. For example one source may go through the loudspeakers, whereas another source may feed a headphone. Additionally other sources like a phone or a navigation system may be mixed to the audio source. In case the 150 MIPS available are not sufficient, a co-dsp (e.g.: TDA7502) may be connected through the serial audio interface (SAI). Finally the device may be embedded into an audio bus system (e.g.: MOST). Following table shows an example of possible modes:
Table 29.
Example of possible modes
Comment DSP1 AM/FM mode Main source and RDS Alternative Rear Source Summed to Main source Alternative Rear Source through SRC Alternative Rear Source CD mode (digital) Alternative Rear Source and RDS Alternative Rear Source Summed to Main source Main source through SRC Alternative Rear Source Available(1) Background recording Available(1) CD Changer mode (analog) Alternative Rear Source and RDS Main source Summed to Main source Alternative Rear Source through SRC Alternative Rear Source Available(1) Background recording Available(1) Tape mode (digital) Alternative Rear Source and RDS Alternative Rear Source Summed to Main source Alternative Rear Source through SRC Main source Available(1) Background recording Available(1) Traffic info play mode Alternative Rear Source and RDS Alternative Rear Source Summed to Main source Alternative Rear Source through SRC Alternative Rear Source Available(1) Main source & Background recording Available(1)
Source AM/FM MPX (analog) CD changer (analog) Phone/Navi (analog) CD/CD ROM audio/MP3 (digital SPDIF) Tape via ADC (digital SAI) DSP co-processor Traffic info storage MOST bus
DSP1 DSP0
DSP1 Dolby B on DSP1
MDSP: master Available (1) CO-dsp: slave DSP0 Background recording
MDSP: slave Co-dsp: slave Available(1) MOST: master
1. The total number of SAI channels is six. They must be split between MOST, Co-DSP and the external ADC for tape. In case of MOST, the DSP clock must be synchronized to the MOST bus.
Note:
The main source (blue) may run in parallel with one of the alternative rear sources (yellow). Phone/Navi, DSP Co-processor, traffic info storage and MOST (green) are available in parallel to all modes.
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Package information
TDA7505
7
Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 14. LQFP100 (14x14x1.4mm) mechanical data and package dimensions
mm DIM. MIN. A A1 A2 b c D D1 D3 E E1 E3 e L L1 K ccc 0.450 0.050 1.350 0.170 0.090 1.400 0.220 TYP. MAX. 1.600 0.150 0.0020 MIN. TYP. MAX. 0.0630 0.0059 inch
OUTLINE AND MECHANICAL DATA
1.450 0.0531 0.0551 0.0571 0.270 0.0067 0.0087 0.0106 0.200 0.0035 0.0079
15.800 16.000 16.200 0.6220 0.6299 0.6378 13.800 14.000 14.200 0.5433 0.5512 0.5591 12.000 0.4724
15.800 16.000 16.200 0.6220 0.6299 0.6378 13.800 14.000 14.200 0.5433 0.5512 0.5591 12.000 0.500 0.600 1.000 0.4724 0.0197 0.750 0.0177 0.0236 0.0295 0.0394
0 (min.), 3.5 (typ.), 7(max.) 0.080 0.003
LQFP100 (14x14x1.40mm) Low profile Quad Flat Package
0086901 D
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Revision history
8
Revision history
Table 30.
Date 23-Oct-2007
Document revision history
Revision 1 Initial release. Changes
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